1. Field of the Invention
The present invention relates generally to processes for depositing doped silicon dioxide in the manufacture of integrated circuit devices. In particular, a method for depositing doped silicon dioxide is provided that improves the etch profile of contact holes etched into the silicon dioxide layer.
2. Description of Related Art
In semiconductor devices, doped silicon dioxide is used to form insulating layers that electrically separate conduction layers from other conduction layers or transistor layers. The conduction layers are electrically connected through the insulating layer by metal filled holes, known as contacts or vias.
When forming the insulating layer, doped silicon dioxide is typically deposited using high density plasma chemical vapor deposition (HDPCVD). Contact holes are etched into the doped silicon dioxide layer with an etchant such as C4F8. A conductive metal such as tungsten is then deposited in the contact holes by chemical vapor deposition or other deposition technique.
The contact holes through the insulating layer must exhibit certain characteristics so that the metal deposited into the contact holes forms a good electrical connection. In particular, the etch profile of the contact holes must be controlled so that the deposited metal fills the holes and makes good contact to the underlying layer.
FIG. 1A is a cross-section of a device layer 105 that exhibits an undesirable etch profile known as “footing.” Footing occurs when the doped silicon dioxide that is in the lower portion 107 of layer 105 is etched at a faster rate than the doped silicon dioxide that is in the upper portion 109 of layer 105.
Footing can cause, among other problems, poor contact between the metal used to fill the contact hole and the conductive layer beneath. For example, as illustrated by contact hole 201 of FIG. 1A, the faster etch rate of the lower portion 107 of doped silicon dioxide layer 105 may create a contact hole 210 with a narrow neck 204. When, as illustrated in FIG. 1B, a metal 212 is put into contact hole 201, the metal 212 may not completely fill hole 201, leaving the regions 214 unfilled. Metal 212 may not make contact, or may make only very poor contact, to the conduction layer 215.
Contact hole 220 of FIG. 2 illustrates another potential etch profile problem that may result in poor contact to the conduction layer 215. The etch of hole 220 progressed horizontally instead of vertically, resulting in an incomplete etch of layer 105. The remaining material 222 of layer 105 prevents a metal from contacting the conductive layer 215 through the hole 220.
The problem of footing is becoming more significant as integrated circuit devices are made smaller and device features are more densely packed. In addition to the above described problems of poor contact, footing widens the contact hole and makes the exact dimensions of the contact hole difficult to control. As device dimensions shrink, the dimension tolerances also shrink, and thus the ability to control the etch profile of contact holes in doped silicon dioxide becomes more important.